\+Heading-1\ Appendix C Instruction set \+helv heading\ Data Processing\+Bold \\-Bold \ \+Helvetica para\ \+Bold \I: Immediate operand bit.\-Bold \ This defines exactly what Operand 2 is. If the I bit is 0, Operand 2 is a register, with the register number held in bits 0 to 3 and the shift applied to that register in bits 4 to 11. If the I bit is 1, Operand 2 is an immediate value, with bits 0 to 7 holding the 8 bit value, and bits 8 to 11 holding the shift applied to that value. \+Bold \S: Set condition codes.\-Bold \ If this bit is set to 0, the condition codes are not altered after the instruction has executed. If it is set to 1, they are altered. \+Bold \Rn: First operand register.\-Bold \ \+Bold \Rd: Destination register.\-Bold \ \+helv heading\ Branch and Branch with link\+Bold \\-Bold \ \+Helvetica para\ \+Bold \L: Link bit.\-Bold \ 0=Branch, 1=Branch with link \+helv heading\ Multiply and multiply-accumulate\+Bold \\-Bold \ \+Helvetica para\ \+Bold \A: Accumulate bit.\-Bold \ 0=multiply, 1=multiply with accumulate \+helv heading\ Single Data transfer\+Bold \\-Bold \ \+Helvetica para\ \+Bold \P: Pre/Post indexing.\-Bold \ 0=post (offset added after transfer). 1=pre (offset added before transfer). \+Bold \U: Up/Down bit.\-Bold \ 0=down (Offset subtracted from base). 1=Up (Offset added to base). \+Bold \B: Byte/Word bit.\-Bold \ 0=transfer word, 1=transfer byte. \+Bold \W: Write-back.\-Bold \ 0=No write back, 1=Write address into base. \+helv heading\ Block data transfer\+Bold \\-Bold \ \+Helvetica para\ \+Bold \S: PSR & Force user mode.\-Bold \ 0=do not load PSR or force user mode. 1=load PSR or force user mode. \+helv heading\ Software Interrupt\+Bold \\-Bold \ Co-processor data operations\+Bold \\-Bold \ \+Helvetica para\ \+Bold \CP Opc: \-Bold \Co-processor operation code. \+Bold \CRn:\-Bold \ Co-processor operand register. \+Bold \CRd:\-Bold \ Co-processor destination register. \+Bold \CP#:\-Bold \ Co-processor number. \+Bold \CP:\-Bold \ Co-processor information \+helv heading\ Co-processor data transfers\+Bold \\-Bold \ \+Helvetica para\ \+Bold \N: Transfer Length.\-Bold \ \+helv heading\ Co-processor register transfers\+Bold \\-Bold \ \+Helvetica para\ \+Bold \L: Load/Store b\-Bold \\+Bold \it.\-Bold \ 0=Store to co-processor, 1=Load from co-processor. \+helv heading\ Undefined instructions. \+Helvetica 12 pt\ \+Bold \Cond: \-Bold \\+Force Normal\Condition field\-Force Normal\ 0000 EQ (EQual) 0001 NE (NEver) 0010 CS (Carry Set) 0011 CC (Carry Clear) 0100 MI (MInus) 0101 PL (PLus) 0110 VS (oVerflow Set) 0111 VC (oVerflow Clear) 1000 HI (HIgher) 1001 LS (Lower or Same) 1010 GE (Greater or Equal) 1011 LT (Less Than) 1100 GT (Greater Than) 1101 LE (Less than or Equal) 1110 AL (ALways) 1111 NV (NeVer) \+Bold \OpCode:\-Bold \ \+Force Normal\Operation code\-Force Normal\ 0000 AND 0001 EOR 0010 SUB 0011 RSB 0100 ADD 0101 ADC 0110 SBC 0111 RSC 1000 TST 1001 TEQ 1010 CMP 1011 CMN 1100 ORR 1101 MOV 1110 BIC 1111 MVN